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KS57C0002/0004
4-BIT CMOS Microcontroller
Product Specification
OVERVIEW
The KS57C0002/0004 single-chip CMOS microcontroller is designed for high-performance using Samsung's newest 4-bit CPU core. With a four-channel comparator, eight LED direct drive pins, serial I/O interface, and a versatile 8-bit timer/countkxcellent design solution for a variety of general-purpose applications. Up to 24 pins of the 30-pin SDIP package can be dedicated to I/O. Five vectored interrupts provide fast response to internal and external events. In addition, the KS57C0002/0004's advanced CMOS technology ensures low power consumption and a wide operating voltage range.
FEATURES
Memory * 256 x 4-bit data memory (KS57C0002) 512 x 4-bit data memory (KS57C0004) 2048 x 8-bit program memory (KS57C0002) 4096 x 8-bit program memory (KS57C0004) Watch Timer * * Interval generation: 0.5 s, 3.9ms at 32768 Hz Four frequency outputs to the BUZ pin * Stop mode (system clock stops)
Oscillation Sources * Crystal, ceramic, or RC for system clock (RC is only for the KS57C0002) Crystal, ceramic: 4.19 MHz (typical) RC: 1 MHz CPU clock divider circuit (by 4, 8, or 64) 0.95, 1.91, 15.3 s at 4.19 MHz
*
8-Bit Serial I/O Interface * * * * 8-bit transmit/receive mode 8-bit receive-only mode LSB-first or MSB-first transmission selectable Internal or external clock source
* * *
24 I/O Pins * * I/O: 18 pins, including 8 highcurrent pins Input only: 6 pins
Instruction Execution Times *
Comparator * 4-channel mode with internal reference (4-bit resolution) and 16-step variable reference voltage 3-channel mode with external reference 150 mV resolution (minimum)
Bit Sequential Carrier * Support for 16-bit serial data transfer in arbitrary format
Operating Temperature * - 40 C to 85 C Operating Voltage Range * 2.7 V to 6.0 V
* *
Interrupts * * * Two external interrupt vectors Three internal interrupt vectors Two quasi-interrupts
8-Bit Basic Timer * Programmable interval timer
Package Type * 30 SDIP, 32 SOP
Memory-Mapped I/O Structure * Data memory bank 15
8-Bit Timer/Counter * * * Programmable interval timer External event counter function Timer/counter clock output to TCLO0 pin
Power-Down Modes * Idle mode (only CPU clock stops)
2-1
KS57C0002 /0004 MICROCONTROLLER
PRODUCT SPECIFICATION
BASIC TIMER
WATCH TIMER
RESET
Xin
Xout P0.0 / SCK P0.1 / SO P0.2 / SI
8-BIT TIMER/ COUNTER
INTERRUPT CONTROL BLOCK
I/O PORT 0 CLOCK STACK POINTER
P3.0 / TCL0 P3.1 / TCLO0 P3.2 / CLO
I/O PORT 3 INTERNAL INTERRUPTS I/O PORT 4 I/O PORT 5 ARITHMETIC LOGIC UNIT I/O PORT 6 INSTRUCTION DECODER
PROGRAM COUNTER
SERIAL I/O PORT INPUT PORT 1
P4.0-P4.3 P5.0-P5.3
PROGRAM STATUS WORD
P1.0 / INT0 P1.1 / INT1 P2.0 / CIN0 P2.1 / CIN1 P2.2 / CIN2 P2.3 / CIN3
INPUT PORT 2 FLAGS
COMPARATOR
P6.0 / KS0 P6.1 / KS1 P6.2 / KS2 P6.3 / BUZ
256 / 512 x 4-BIT DATA MEMORY
2 K/ 4 K BYTE PROGRAM MEMORY
a
Figure 1. KS57C0002/0004 Block Diagram
P0.0 /
SCK
A
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
30 29 28 27 26 25
VDD P6.3 / BUZ P6.2 / KS2 P6.1 / KS1 P6.0 / KS0 P5.3 P5.2 P5.1 P5.0 P4.3 P4.2 P4.1 P4.0 Xout Xin
P0.0/SCK P0.1/SO P0.2/SI P1.0/INT0 NC P1.1/INT1 P2.0/CIN0 P2.1/CIN1 P2.2/CIN2 P2.3/CIN3 P3.0/TCL0 P3.1/TCLO0 P3.2/CLO
RESET
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27
VDD P6.3/BUZ P6.2/KS2 P6.1/KS1 P6.0/KS0 P5.3 P5.2 P5.1 P5.0 P4.3 P4.2 NC P4.1 P4.0 Xout Xin
P0.1 / SO P0.2 / SI P1.0 / INT0 P1.1 / INT1 P2.0 / CIN0 P2.1 / CIN1 P2.2 / CIN2 P2.3 / CIN3 P3.0 / TCL0 P3.1 / TCLO0 P3.2 / CLO
RESET
KS57C0002/04 (Top View)
24 23 22 21 20 19 18 17 16
KS57C0002/04 25 (Top View)
24 23 22 21 20 19 18 17
26
TEST VSS
TEST VSS
30 SDIP
32 SOP
Figure 2. KS57C0002/0004 Pin Assignments (32 SOP, 30 SDIP)
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PRODUCT SPECIFICATION
KS57C0002 /0004 MICROCONTROLLER
Table 1. KS57C0002/0004 Pin Descriptions Pin Name P0.0 P0.1 P0.2 Pin Type I/O Description 3-bit I/O port. 1-bit or 3-bit read/write and test is possible. Pull-up resistors are assignable to input pins by software and are automatically disabled for output pins. Pins are individually configurable as input or output. 2-bit input port. 1-bit or 2-bit read and test is possible. Pull-up resistors are assignable by software. 4-bit input port. 1-bit or 4-bit read and test is possible. Same as port 0 Number 1 2 3 Share Pin
SCK
SO SI
P1.0 P1.1 P2.0-P2.3 P3.0 P3.1 P3.2 P4.0-P4.3 P5.0-P5.3
I I I/O
4 5 6-9 10 11 12 18-21 22-25
INT0 INT1 CIN0-CIN3 TCL0 TCLO0 CLO --
I/O
4-bit I/O ports. 1-, 4-, or 8-bit read/write and test is possible. Pins are individually configurable as input or output. Ports can be configurable as n-channel open-drain by mask option (maximum 9V). 4-bit I/O port. 1-bit or 4-bit read/write and test is possible. Pull-up resistors are assignable to input pins by software and are automatically disabled for output pins. Pins individually configurable as input or output. External interrupts with rising/falling edge detection External interrupts with rising/falling edge detection 4-channel comparator input. CIN0-CIN2: comparator input only. CIN3: comparator input or external reference input Serial interface clock signal Serial data output Serial data input External clock input for timer/counter Timer/counter clock output CPU clock output 2 kHz, 4 kHz, 8 kHz, or 16 kHz frequency output at 4.19 MHz for buzzer sound Quasi-interrupt input with falling edge detection Main power supply Ground Reset signal Test signal input (must be connected to VSS) Crystal, ceramic, or RC oscillator signal for system clock
P6.0 P6.1 P6.2 P6.3 INT0 INT1 CIN0-CIN3
I/O
26 27 28 29 4 5 6-9
KS0 KS1 KS2 BUZ P1.0 P1.1 P2.0-P2.3
I I I
SCK
I/O I/O I/O I/O I/O I/O I/O I/O -- -- I I --
1 2 3 10 11 12 29 26-28 30 15 13 14 16, 17
P0.0 P0.1 P0.2 P3.0 P3.1 P3.2 P6.3 P6.0-P6.2 -- -- -- -- --
SO SI TCL0 TCLO0 CLO BUZ KS0-KS2 V DD V SS
RESET
TEST X in, Xout
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KS57C0002 /0004 MICROCONTROLLER
PRODUCT SPECIFICATION
Table 2. Supplemental KS57C0002/0004 Pin Data Pin Numbers 1, 2, 3 4, 5 6-9 10-12 13 14 15 16, 17 18-21 22-25 26-29 30 Pin Names P0.0-P0.2 P1.0, P1.1 P2.0-P2.3 P3.0-P3.2
RESET
Share Pins
SCK,
I/O Type I/O I I I/O I I -- -- I/O I/O I/O --
Reset Value Input Input Input Input -- -- -- -- Input Input Input --
Circuit Type 5 3 6, 8 * 5 9 -- -- -- 7 7 5 --
SO, SI
INT0, INT1 CIN0-CIN3 TCL0, TCLO0, CLO
--
--
TEST V SS Xin, Xout P4.0-P4.3 P5.0-P5.3 P6.0-P6.3 V DD
I/O circuit type 8 is for P2.3 only.
-- -- -- -- KS0, KS1, KS2, BUZ --
*
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PRODUCT SPECIFICATION
KS57C0002 /0004 MICROCONTROLLER
VDD
VDD
P-CHANNEL DATA IN N-CHANNEL OUTPUT DISABLE
P-CHANNEL OUT N-CHANNEL
Figure 3. Pin Circuit Type 1
Figure 6. Pin Circuit Type 4 VDD
PULL-UP RESISTOR RESISTOR ENABLE DATA OUTPUT DISABLE
IN
P-CHANNEL
SCHMITT TRIGGER
CIRCUIT TYPE 4
I/O
CIRCUIT TYPE 2
Figure 4. Pin Circuit Type 2 VDD
PULL-UP RESISTOR RESISTOR ENABLE
Figure 7. Pin Circuit Type 5
DIGITAL INPUT
P-CHANNEL
ANALOG INPUT IN SCHMITT TRIGGER
Figure 5. Pin Circuit Type 3
Figure 8. Pin Circuit Type 6
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KS57C0002 /0004 MICROCONTROLLER
PRODUCT SPECIFICATION
VDD
P-CHANNEL DATA (MASK OPTION)
DIGITAL INPUT
ANALOG INPUT N-CHANNEL OUTPUT DISABLE EXTERNAL VREF
MAXIMUM INPUT VOLTAGE: 9 V
Figure 9. Pin Circuit Type 7
Figure 10. Pin Circuit Type 8
VDD
IN
Schmitt Trigger Input
Figure 11. Pin Circuit Type 9
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PRODUCT SPECIFICATION
KS57C0002 /0004 MICROCONTROLLER
PROGRAM MEMORY (ROM)
ROM maps for KS57C0002/0004 devices are mask programmable at the factory. In their standard configuration, the device's 2048 x 8-bit (KS57C0002), or 4096 x 8-bit (KS57C0004) program memory has four areas that are directly addressable by the program counter ( PC):
-- 16-byte general-purpose area -- 16-byte area for vector addresses -- 96-byte instruction reference area -- 1920-byte (KS57C0002), 3968-byte (KS57C0004) general-purpose area
0000H VECTOR ADDRESS AREA 000FH 0010H GENERAL-PURPOSE AREA 001FH 0020H INSTRUCTION REFERENCE AREA 007FH 0080H GENERAL-PURPOSE AREA 1
7 0000H
6
5
4
3
2
1
0
RESET
0002H
INTB
0004H
INT0
0006H
INT1
KS57C0002 07FFH KS57C0004 0800H
0008H
INTS
000AH
GENERAL-PURPOSE AREA 2
INTT0
0FFFH
Figure 12. ROM Map
Figure 13. Vector Address Map
DATA MEMORY (RAM)
In its standard configuration, the 256x 4 -bit (KS57C0002), or the 512 x4-bit (KS57C0004) data memory has four areas: -- 32 x4-bit working registers -- 224x 4-bit general-purpose area in bank0 which is also used as the stack area
-- 256x4 -bit general-purpose area in bank1 (KS57C0004 only) -- 128x 4-bit area in bank 15 for memory-mapped I/O addresses I/O MAP FOR HARDWARE REGISTERS Table 3 contains detailed information about I/O mapping for peripheral hardware in bank 15 (register locations F80H-FFFH).
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KS57C0002 /0004 MICROCONTROLLER
PRODUCT SPECIFICATION
ADDRESSING MODE RAM AREAS 000 H 01FH 020 H 07FH 080 H WORKING REGISTERS BANK 0 (GENERAL REGISTERS AND STACK)
DA DA.b EMB = 0 EMB = 1
@HL @H + DA.b EMB = 0 EMB = 1
@WX @WL X
mema.b
memb.@L
X
X
SMB = 0
SMB = 0
0FFH 100 H BANK 1 KS57C0004 ONLY (GENERAL REGISTERS) 1FFH F80H BANK 15 (PERIPHERAL HARDWARE REGISTERS) FB0H FBFH FC0H SMB = 15 SMB = 15 FF0H FFFH NOTES: 1. 'X' means don't care. 2. Blank columns indicate RAM areas that are not addressable, given the addressing method and enable memory bank (EMB) flag setting shown in the column headers.
SMB = 1
SMB = 1
Figure 14. Data Memory (RAM) Address Structure
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PRODUCT SPECIFICATION
KS57C0002 /0004 MICROCONTROLLER
Table 3. I/O Map for Memory Bank 15 Memory Bank 15 Address F81H-F80H F85H F87H-F86H F89H-F88H F91H-F90H F95H-F94H F97H-F96H FB0H FB1H FB2H FB3H FB4H FB5H FB6H FB8H FBAH FBCH FBDH FBEH FBFH FC0H FC1H FC2H FC3H FD0H FD4H FD7H-FD6H FDDH-FDCH FE1H-FE0H FE2H FE5H-FE4H FE9H-FE8H FEBH-FEAH BSC0 BSC1 BSC2 BSC3 CLMOD CMPREG CMOD PUMOD SMOD P2MOD SBUF PMG1 PMG2 IPR PCON IMOD0 IMOD1 IMODK Register SP BMOD BCNT WMOD TMOD0 TCNT0 TREF0 PSW Name Stack Pointer Basic Timer Mode Register Basic Timer Counter Register Watch Timer Mode Register Timer/Counter 0 Mode Register Timer/Counter 0 Counter Register Timer/Counter 0 Reference Reg IS1 C (2) IS0 SC2 EMB SC1 ERB SC0 R/W R/W W R W W R W R/W R W W W W W R/W R/W R/W Addressing Mode 1-Bit No .3 No No .3 No No Yes No IME No No No No Yes Yes Yes 4-Bit No Yes No No No No No Yes No Yes Yes Yes Yes Yes Yes Yes Yes No No No No No No No No 8-Bit Yes No Yes Yes Yes Yes Yes Yes
SIO Mode Register Power Control Register External Interrupt 0 Mode Register External Interrupt 1 Mode Register External Key Interrupt Mode Reg "0" "0" "0" "0" IE1 "0" "0" "0" "0" "0" IRQ1 "0" IEB IEW IET0 IES IE0 IEK IRQB IRQW IRQT0 IRQS IRQ0 IRQK
Bit Sequential Carrier 0 Bit Sequential Carrier 1 Bit Sequential Carrier 2 Bit Sequential Carrier 3 Clock Mode Register Comparison Result Register Comparator Mode Register Pull-up Mode Register SIO Mode Register Port 2 Mode Register SIO Buffer Register Port Mode Group 1 Port Mode Group 2
R/W
Yes
Yes
Yes
W R R/W W W W R/W W
No No No No .3 No No No
Yes Yes No No No Yes No No
No No Yes Yes Yes No Yes Yes
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KS57C0002 /0004 MICROCONTROLLER
PRODUCT SPECIFICATION
Table 3. I/O Map for Memory Bank 15 (Concluded) Memory Bank 15 Address FEDH-FECH FF0H FF1H FF2H FF3H FF4H FF5H FF6H Register PMG3 P0 P1 P2 P3 P4 P5 P6 Name Port Mode Group 3 Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 R/W W R/W R R R/W R/W R/W R/W No Addressing Mode 1-Bit No Yes 4-Bit No Yes 8-Bit Yes No No No No Yes
NOTES: 1. Bit 0 in the WMOD register must be set to "0". 2. The carry flag can be read or written by specific bit manipulation instructions only.
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PRODUCT SPECIFICATION
KS57C0002 /0004 MICROCONTROLLER
BIT SEQUENTIAL CARRIER (BSC)
The bit sequential carrier (BSC) is a 16-bit general register that is mapped in data memory bank 15. Using the BSC, you can specify sequential addresses and bit locations using 1-bit indirect addressing (memb.@L). BSC bit addressing is independent of the current EMB value. In this way, programs can process 16-bit data by moving the bit location sequentially and then Table 4. BSC Register Organization Name BSC0 BSC1 BSC2 BSC3 Address FC0H FC1H FC2H FC3H Bit 3 BSC0.3 BSC1.3 BSC2.3 BSC3.3
incrementing or decrementing the value of the L register. For 8-bit manipulations, the 4-bit register names BSC0 and BSC2 must be specified and the upper and lower 8 bits manipulated separately. If the values of the L register are 0H at BSC0.@L, the address and bit location assignment is FC0H.0. If the L register content is FH at BSC0.@L, the address and bit location assignment is FC3H.3.
Bit 2 BSC0.2 BSC1.2 BSC2.2 BSC3.2
Bit 1 BSC0.1 BSC1.1 BSC2.1 BSC3.1
Bit 0 BSC0.0 BSC1.0 BSC2.0 BSC3.0
PROGRAMMING TIP -- Using the BSC Register to Output 16-Bit Data
To use the bit sequential carrier (BSC) register to output 16-bit data (5937H) to the P3.0 pin: BITS EMB SMB 15 LD EA,#37H LD BSC0,EA LD EA,#59H LD BSC2,EA SMB 0 LD L,#0H C,BSC0.@L LDB P3.0,C INCS L JR AGN RET
; ; ; ; ; ; ;
BSC0 A, BSC1 E BSC2 A, BSC3 E
AGN LDB
P3.0 C
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KS57C0002 /0004 MICROCONTROLLER
PRODUCT SPECIFICATION
INTERRUPTS
The KS57C0002/0004 microcontroller has two external interrupts, three internal interrupts, and two quasiinterrupts. Table 5 shows the conditions for each interrupt generation. The request flags that actually generate these interrupts are cleared by hardware when the service routine is vectored. However, the quasi-interrupt's request flags must be cleared by software.
IMOD1
IMOD0
IEK
IEW
IET0
IES
IE1
IE0
IEB
INTB INT0 INT1
IRQB IRQ0 IRQ1
# @
@
INTS INTT0 INTW INTK (KS0-KS2) IMODK
IRQS IRQT0 IRQW IRQK
POWER-DOWN MODE RELEASE SIGNAL
IME
IPR
INTERRUPT CONTROL UNIT
IS1 IS0
# = Noise filtering circuit @ = Edge detection circuit
VECTOR INTERRUPT GENERATOR
Figure 15. Interrupt Control Circuit Diagram
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PRODUCT SPECIFICATION
KS57C0002 /0004 MICROCONTROLLER
Table 5. Interrupt Request Flag Conditions and Priorities Interrupt Source INTB INT0 INT1 INTS INTT0 INTK * INTW * * Internal / External I E E I I E I Condition for IRQx Flag Setting Reference time interval signal from basic timer Rising or falling edge detected at INT0 pin Rising or falling edge detected at INT1 pin Completion signal for serial transmit-and-receive or receive-only operation Signals for TCNT0 and TREF0 registers match Falling edge is detected at any of the KS0-KS2 pins Time interval of 0.5 s or 3.19 ms Interrupt Priority 1 2 3 4 5 -- -- Request Flag Name IRQB IRQ0 IRQ1 IRQS IRQT0 IRQK IRQW
The INTK and INTW are quasi-interrupts and INTK are used only for testing incoming signals.
INTERRUPT ENABLE FLAGS (IEx) IEx flags, when set to "1", enable specific interrupt requests to be serviced. When the interrupt request flag is set to "1", an interrupt will not be serviced until its corresponding IEx flag is also enabled. The IPR register contains a global disable bit, IME, which disables all interrupt at once. Table 6. Interrupt Enable and Request Flag Address FB8H FBAH FBBH FBCH FBDH FBEH FBFH Bit 3 0 0 0 0 0 IE1 0 Bit 2 0 0 0 0 0 IRQ1 0 Bit 1 IEB IEW 0 IET0 IES IE0 IEK Bit 0 IRQB IRQW 0 IRQT0 IRQS IRQ0 IRQK
INTERRUPT PRIORITY Each interrupt source can also be individually programmed to high levels by modifying the IPR register. When IS1 = 0 and IS0 = 1, a low-priority interrupt can itself be interrupted by a high-priority interrupt, but not by another low-priority interrupt. If you clear the interrupt status flags (IS1 and IS0) to "0" in a interrupt service routine, a high-priority interrupt can be interrupted by low-priority interrupt (multi-level interrupt). Before the IPR can be modified by 4-bit write instructions, all interrupts must first be disabled by a DI instruction. When all interrupts are low priority (the lower three bits of the IPR register are "0"), the interrupt requested first will have high priority. Therefore, the first-requested interrupt cannot be superseded by any other interrupt. If two or more interrupt requests are received simultaneously, the priority level is determined according to the standard interrupt priorities, where the default priority is assigned by hardware when the lower three IPR bits = "0".
NOTES: 1. IEx refers to all interrupt enable flags. 2. IRQx refers to all interrupt request flags. 3. IEx = "0" is interrupt disable mode. 4. IEx = "1" is interrupt enable mode.
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KS57C0002 /0004 MICROCONTROLLER
PRODUCT SPECIFICATION
In this case, the higher-priority interrupt request is serviced and the other interrupt is inhibited. Then, when the high-priority interrupt is returned from its service routine by an IRET instruction, the inhibited service routine is started. Table 7. Interrupt Priority Register Settings IPR.2 0 0 0 0 1 1 IPR.1 0 0 1 1 0 0 IPR.0 0 1 0 1 0 1 Result of IPR Bit Setting Process all interrupt requests at low priority. INTB INT0 INT1 INTS INTT0
EXTERNAL INTERRUPTS The external interrupt mode registers (IMOD0 and IMOD1) are used to control the triggering edge of the input signal at the INT0 and INT1 pins, respectively. When a sampling clock rate of fx/64 is used for INT0, an interrupt request flag must be cleared before 16 machine cycles have elapsed. Since the INT0 pin has a clock-driven noise filtering circuit built into it, please take the following precautions when you use it: -- To trigger an interrupt, the input signal width at INT0 must be at least two times wider than the pulse width of the clock selected by IMOD0. This is true even when the INT0 pin is used for general-purpose input. -- Since the INT0 input sampling clock does not operate during Stop or Idle mode, you cannot use INT0 to release power-down mode. When modifying the IMOD0 and IMOD1 registers, it is possible to accidentally set an interrupt request flag.
Table 8. Default Priorities Source INTB INT0 INT1 INTS INTT0 1 2 3 4 5 Default Priority
To avoid unwanted interrupts, take these precautions when writing your programs: 1. Disable all interrupts with a DI instruction. 2. Modify the IMOD0 or IMOD1 register. 3. Clear all relevant interrupt request flags. 4. Enable the interrupt by setting the appropriate IEx flag. 5. Enable all interrupts with an EI instructions.
Table 9. IMOD0 and IMOD1 Register Organization (4-Bit W) IMOD0.3 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 0 1 IMOD1.0 0 1 0 IMOD0.1 IMOD0.0 Effect of IMOD0 Settings Select CPU clock for sampling Select fx/64 sampling clock Rising edge detection Falling edge detection Both rising and falling edge detection IRQ0 flag cannot be set to "1" Effect of IMOD1 Settings Rising edge detection Falling edge detection
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PRODUCT SPECIFICATION
KS57C0002 /0004 MICROCONTROLLER
EXTERNAL KEY INTERRUPT MODE REGISTER The external key interrupt (INTK) mode register, IMODK, is used to select KS pins as interrupt input pins. When a falling edge is detected at one of the KS0-KS2 pins, the IRQK flag is set to "1". This generates an interrupt request and a release signal for power-down mode. To generate a key interrupt on a falling signal edge at KS0- KS2, all of the KS0-KS2 pins must be configured to input mode. If one or more of the pins which are configured as key Interrupt (KS0-KS2) are in Low input or Low output state, the key Interrupt can not be occurred. Table 10. IMODK Register Bit Settings (4-Bit W) 0 0 0 0 0 0 0 0 0 IMODK.2 0 0 0 0 1 1 1 1 IMODK.1 0 0 1 1 0 0 1 1 IMODK.0 0 1 0 1 0 1 0 1 Effect of IMODK Settings Disable key interrupt Select falling edge at KS0 Select falling edge at KS1 Select falling edge at KS0-KS1 Select falling edge at KS2 Select falling edge at KS0, KS2 Select falling edge at KS1-KS2 Select falling edge at KS0-KS2
KS2 KS1 KS0 FALLING EDGE DETECTION CIRCUIT IMODK IRQK
NOTE: To generate a key interrupt on a falling edge at KS0-KS2, all KS0-KS2 pins must be configured to input mode. Figure 15-1. Circuit diagram for KS0-KS2 Pins
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KS57C0002 /0004 MICROCONTROLLER
PRODUCT SPECIFICATION
OSCILLATOR CIRCUITS
The KS57C0002/0004 system clock circuit is shown in Figure 16 below. By manipulating bits 1 and 0 of the PCON register, the system clock frequency can be divided by 4, 8, or 64.
SYSTEM OSCILLATOR CIRCUIT Xin Xout
fx
FREQUENCY DIVIDING CIRCUIT OSCILLATOR STOP
1/2 1/16
WATCH TIMER BASIC TIMER TIMER/COUNTER 0 CLOCK OUTPUT CIRCIT COMPARATOR
SELECTOR
CPU CLOCK
1/4
CPU STOP SIGNAL ( IDLE MODE) PCON.0 PCON.1 IDLE STOP PCON.2 PCON.3 OSCILLATOR CONTROL CIRCUIT WAIT RELEASE SIGNAL INTERNAL RESET SIGNAL POWER-DOWN RELEASE SIGNAL
PCON.3,2 CLEAR Figure 16. Clock Circuit Diagram
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PRODUCT SPECIFICATION
KS57C0002 /0004 MICROCONTROLLER
Xin
Xin
Xin R
Xout Xout
Xout
Figure 17. Crystal/Ceramic Oscillator
Figure 18. External Clock
Figure 19. RC Oscillator (only for the KS57C0002)
POWER CONTROL REGISTER (PCON) The power control register, PCON, is used to select the CPU clock frequency and to control CPU operating and power-down modes. PCON bits 3 and 2 are controlled by the STOP and IDLE instructions, which engage the Stop and Idle power-down modes, respectively. Using these instructions, you can initiate a power-down mode at any time, regardless of the current value of the enable memory bank flag (EMB). Table 11. Power Control Register (PCON) Organization (4-Bit W) PCON Bit Settings PCON.3 0 0 1 PCON.2 0 1 0 Normal CPU operating mode Idle power-down mode Stop power-down mode Resulting CPU Clock Frequency fx/64 fx/8 fx/4 Resulting CPU Operating Mode
PCON Bit Settings PCON.1 0 1 1 PCON.0 0 0 1
PROGRAMMING TIP -- Setting the CPU Clock
To set the CPU clock to 0.95 s at 4.19 MHz: BITS SMB LD LD EMB 15 A,#3H PCON,A
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KS57C0002 /0004 MICROCONTROLLER
PRODUCT SPECIFICATION
INSTRUCTION CYCLE TIMES The unit of time that equals one machine cycle varies depending on how the oscillator clock signal is divided. Table 12. Instruction Cycle Times for CPU Clock Rates Selected CPU Clock fx/64 fx/8 fx/4 Resulting Frequency 65.5 kHz 524.0 kHz 1.05 MHz fx = 4.19 MHz Oscillation Source Cycle Time (s) 15.3 1.91 0.95
CLOCK OUTPUT CIRCUIT The clock output circuit outputs clock pulses to the CLO pin. The clock output mode register, CLMOD, is used to enable or disable clock output to the CLO pin and to select the CPU clock source and frequency. To output a frequency, the clock output pin CLO/P3.2 must be set to output mode and the pin's latch must be cleared to "0". Bit 2 in the CLMOD register must always be "0". Table 13. Clock Output Mode Register (CLMOD) Organization CLMOD Bit Settings CLMOD.1 0 0 1 1 CLMOD.3 0 1 Clock output is disabled Clock output is enabled CLMOD.0 0 1 0 1 Clock Source CPU clock (fx/4, fx/8, fx/64) fx/8 fx/16 fx/64 Result of CLMOD.3 Setting Resulting Clock Output Frequency 1.05 MHz, 524 kHz, 65.5 kHz 524 kHz 262 kHz 65.5 kHz
NOTE: Frequencies assume that fx = 4.19 MHz.
CLMOD.3 CLMOD.2 4 CLMOD.1 CLMOD.0 CLOCK SELECT OR P3.2 OUTPUT LATCH PM3.2
C LO
CLOCKS (fx/8, fx/16, fx/64, CPU clock )
Figure 20. CLO Output Pin Circuit Diagram
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PRODUCT SPECIFICATION
KS57C0002 /0004 MICROCONTROLLER
PROGRAMMING TIP -- CPU Clock Output to the CLO Pin
To output the CPU clock to the CLO pin: BITS SMB LD LD BITR LD LD EMB 15 EA,#40H PMG1,EA P3.2 A,#9H CLMOD,A ; ; ; Or BITR EMB P3.2 Output mode Clear P3.2 output latch
POWER-DOWN
The KS57C0002/0004 microcontroller has two powerdown modes to reduce power consumption: Idle and Stop. In Idle mode, the CPU clock stops while peripherals and the oscillator continue to operate normally.
In Stop mode, system clock oscillation is halted (assuming it is currently operating), and peripheral hardware components are powered-down. The effect of Stop mode on specific peripheral hardware components -- CPU, basic timer, serial I/O, timer/ counters 0, and watch timer -- and on external interrupt requests, is detailed in Table 14.
Table 14. Hardware Operation During Power-Down Modes Operation Clock oscillator Basic timer Serial interface Timer/counter 0 Comparator Watch timer External interrupts CPU Power-down mode release signal Stop Mode (STOP) System clock oscillation stops Basic timer stops Operates only if external SCK input is selected as the serial I/O clock Operates only if TCL0 is selected as the counter clock Comparator operation is stopped Watch timer operation is stopped INT1 and INTK are acknowledged; INT0 is not serviced All CPU operations are disabled Idle Mode (IDLE) CPU clock oscillation stops (system clock oscillation continues) Basic timer operates (with IRQB set at each reference interval) Operates if a clock other than the CPU clock is selected as the serial I/O clock Timer/counter 0 operates Comparator operates Watch timer operates INT1 and INTK are acknowledged; INT0 is not serviced All CPU operations are disabled
Interrupt request signals (except INT0) Interrupt request signals (except INT0) are enabled by an interrupt enable flag or are enabled by an interrupt enable flag or by RESET input by RESET input
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PRODUCT SPECIFICATION
RECOMMENDED CONNECTIONS FOR UNUSED PINS To reduce overall power consumption, please configure unused pins according to the guidelines described in Table 15. Table 15. Unused Pin Connections for Reduced Power Consumption Pin/Share Pin Names P0.0 / SCK P0.1 / SO P0.2 / SI P1.0 / INT0 - P1.1 / INT1 P2.0 / CIN0 P2.1 / CIN1 P2.2 / CIN2 P2.3 / CIN3 P3.0 / TCLO0 P3.1 / TCLO1 P3.2 / CLO P3.3 / BUZ P4.0-P4.3, P5.0-P5.3 P6.0 / KS0 - P6.3 / BUZ TEST Recommended Connection Input mode: Connect to VDD Output mode: Do not connect Connect to VDD Connect to VDD
Input mode: Connect to VDD Output mode: Do not connect
Connect to VSS
RESET
Table 16 provides detailed information about hardware register values after a RESET occurs during power-down mode or during normal operation. Table 16. Hardware Register Values After Hardware Component or Subcomponent Program counter (PC)
RESET
If RESET Occurs During Power-Down Mode
If RESET Occurs During Normal Operation
Lower three bits of address 0000H Lower three bits of address 0000H are transferred to PC10-8, and the are transferred to PC10-8, and the contents of 0001H to PC7-0. contents of 0001H to PC7-0.
Program Status Word (PSW): Carry flag (C) Skip flag (SC0-SC2) Interrupt status flags (IS0, IS1) Bank enable flags (EMB, ERB) Retained 0 0 Bit 6 of address 0000H in program memory is transferred to the ERB flag, and bit 7 of the address to the EMB flag. Undefined Undefined 0 0 Bit 6 of address 0000H in program memory is transferred to the ERB flag, and bit 7 of the address to the EMB flag. Undefined
Stack pointer (SP)
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PRODUCT SPECIFICATION
KS57C0002 /0004 MICROCONTROLLER
Table 16. Hardware Register Values After Hardware Component or Subcomponent Data Memory (RAM): General registers E, A, L, H, X, W, Z, Y General-purpose registers Bank selection registers (SMB, SRB) BSC register (BSC0-BSC3) Clocks: Power control register (PCON) Clock output mode register (CLMOD) Interrupts: Interrupt request flags (IRQx) Interrupt enable flags (IEx) Interrupt priority flag (IPR) Interrupt master enable flag (IME) INT0 mode register (IMOD0) INT1 mode register (IMOD1) INTK mode register (IMODK) I/O Ports: Output buffers Output latches Port mode flags (PM) Pull-up resistor mode reg (PUMOD) Port 2 mode register (PWMOD) Basic Timer: Count register (BCNT) Mode register (BMOD) Timer/Counter 0: Count registers (TCNT0) Reference registers (TREF0) Mode registers (TMOD0) Output enable flags (TOE0)
RESET
(Continued) If RESET Occurs During Normal Operation
If RESET Occurs During Power-Down Mode
Values retained Values retained (Note 1) 0, 0 0
Undefined Undefined 0, 0 0
0 0
0 0
0 0 0 0 0 0 0
0 0 0 0 0 0 0
Off 0 0 0 0
Off 0 0 0 0
Undefined 0
Undefined 0
0 FFH, FFFFH 0 0
RESET
0 FFH, FFFFH 0 0
signal is input.
Note1: The values of the 0F8H-0FDH are not retained when a
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PRODUCT SPECIFICATION
Table 16. Hardware Register Values After Hardware Component or Subcomponent Watch Timer: Watch timer mode register (WMOD) Comparator Comparator mode register (CMOD) Comparison result register Serial I/O Interface: SIO mode register (SMOD) SIO interface buffer (SBUF)
RESET
(Continued) If RESET Occurs During Normal Operation
If RESET Occurs During Power-Down Mode
0
0
0 Undefined
0 Undefined
0 Values retained
0 Undefined
I/O PORTS
The KS57C0002/0004 has two input ports and five I/O ports. There are total of 6 input pins and 18 configurable I/O pins, including 8 high-current I/O pins. This gives a total number of 24 I/O pins.
PORT MODE FLAGS (PM FLAGS) Port mode flags (PM) are used to configure I/O ports 0 and 3-6 to input or output mode. It does this by setting or clearing the corresponding I/O buffer. If a PM bit is "0", the corresponding I/O pin is set to input mode. If the PM bit is "1", the corresponding pin is set to output mode.
Table 17. Port Mode Flag Map PM Group ID PMG1 PMG2 PMG3 Address FE8H FE9H FEAH FEBH FECH FEDH Bit 3 "0" "0" PM4.3 "0" PM5.3 PM6.3 Bit 2 PM0.2 PM3.2 PM4.2 "0" PM5.2 PM6.2 Bit 1 PM0.1 PM3.1 PM4.1 "0" PM5.1 PM6.1 Bit 0 PM0.0 PM3.0 PM4.0 "0" PM5.0 PM6.0
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KS57C0002 /0004 MICROCONTROLLER
PROGRAMMING TIP -- Configuring I/O Ports as Input or Output
Configure P0.0 and P3.0 as an output port and the other ports as input ports: BITS SMB LD LD LD LD LD LD EMB 15 EA,#11H PMG1,EA EA,#00H PMG2,EA EA,#00H PMG3,EA
; ; ;
P0.0 and P3.0 Output P4 Input P5, P6 Input
PORT 2 MODE REGISTER (P2MOD) P2MOD register settings determine if port 2 is used either for analog input or for digital input. FE2H P2MOD.3 P2MOD.2 P2MOD.1 4-Bit W P2MOD.0
PULL-UP RESISTOR MODE REGISTER (PUMOD) The pull-up resistor mode register, PUMOD, is used to assign internal pull-up resistors to specific I/O ports. When a configurable I/O port pin is used as an output pin, its assigned pull-up resistor is automatically disabled, even though the pin's pull-up is enabled by a corresponding PUMOD bit setting. When bit = "1", a pull-up resistor is assigned to the corresponding I/O port: PUMOD.3 for port 3, PUMOD.6 for port 6, and so on.
When a P2MOD bit is set to "1", the corresponding pin is configured as a digital input pin. When set to "0", configured as an analog input pin: P2MOD.0 for P2.0, P2MOD.1 for P2.1, P2MOD.2 for P2.2, and P2MOD.3 for P2.3.
Table 18. Pull-Up Resistor Mode Register (PUMOD) Organization (8-Bit W) Address FDCH FDDH Bit 3 PUMOD.3 "0" Bit 2 "0" PUMOD.6 Bit 1 PUMOD.1 "0" Bit 0 PUMOD.0 "0"
PROGRAMMING TIP -- Enabling and Disabling I/O Port Pull-Up Resistors
P6 enable pull-up resistors, P0, P1, and P3 disable pull-up resistors. BITS SMB LD LD EMB 15 EA,#40H PUMOD,EA
;
P6 enable
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PRODUCT SPECIFICATION
PORT 0 CIRCUIT DIAGRAM
SCK
P0.0
LATCH
SMOD.1 SO
P0.1
LATCH
P0.2
LATCH
SMOD.7 SMOD.6 SMOD.5
V DD
SCK
PUMOD.0
SI
PM0.2
PM0.1
PM0.0
P0.0 / SCK P0.1 / SO P0.2 / SI
NOTE: When a port pin acts as an output, its pull-up resistor is automatically disabled, even though the port's pull-up resistor is enabled by bit settings to the pull-up resistor mode register (PUMOD).
Figure 21. I/O Port 0 Circuit Diagram
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PRODUCT SPECIFICATION
KS57C0002 /0004 MICROCONTROLLER
PORT 1 CIRCUIT DIAGRAM VDD PUMOD.1
IMOD0
VDD
INT0
INT1
P1.0 / INT0 P1.1 / INT1
N/R = Noise reduction
N/R Circuit
Figure 22. Input Port 1 Circuit Diagram PORT 2 CIRCUIT DIAGRAM
P2.0 / CIN0
DIGITAL INPUT
ANALOG INPUT P2.1 / CIN1 DIGITAL INPUT
ANALOG INPUT P2.2 / CIN2 DIGITAL INPUT
ANALOG INPUT P2.3 / CIN3 DIGITAL INPUT
ANALOG INPUT EXTERNAL REFERENCE Figure 23. Port 2 Circuit Diagram
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PRODUCT SPECIFICATION
PORT 3 CIRCUIT DIAGRAM
V DD
PUMOD.3
TC0 CLOCK OUTPUT CLOCK OUTPUT
PM3.2
PM3.1
PM3.0
P3.0 / TCL0 P3.1 / TCLO0 P3.2 / CLO OUTPUT LATCH 1, 4
M U X 1, 4
TCL0 NOTE: When a port pin acts as an output, its pull-up resistor is automatically disabled, even though the port's pull-up resistor is enabled by bit settings to the pull-up resistor mode register (PUMOD).
Figure 24. Port 3 Circuit Diagram
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PRODUCT SPECIFICATION
KS57C0002 /0004 MICROCONTROLLER
PORTS 4 AND 5 CIRCUIT DIAGRAM
V DD
P-CH
x = 4, 5 b = 0, 1, 2, 3
PMx.b
8
MASK OPTION
Px.b
OUTPUT LATCH
1, 4, 8
N-CH
M VSS U X
Figure 25. Circuit Diagram for Ports 4 and 5
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PRODUCT SPECIFICATION
PORT 6 CIRCUIT DIAGRAM
V DD
PUMOD.6
PM6.3
PM6.2
PM6.1
PM6.0
P6.0 / KS0 P6.1 / KS1 P6.2 / KS2 P6.3 / BUZ
OUTPUT LATCH
1, 4
M U X 1, 4
NOTE: When a port pin acts as an output, its pull-up resistor is automatically disabled, even though the port's pull-up resistor is enabled by bit settings to the pull-up resistor mode register (PUMOD).
Figure 26. Port 6 Circuit Diagram
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PRODUCT SPECIFICATION
KS57C0002 /0004 MICROCONTROLLER
BASIC TIMER (BT)
The basic timer generates interrupt requests atprecise intervals. You can use the basic timer as a "watchdog" timer for monitoring system events or use BT output to stabilize clock oscillation when Stop mode is released by an interrupt and following RESET. Interval Timer Function The measurement of elapsed time intervals is the basic timer's primary function. The standard interval is 256 BT clock pulses. To restart the basic timer, set bit 3 of the mode register BMOD to "1". The 8-bit counter register, BCNT, is incremented each time a clock signal is detected that corresponds to the frequency selected by BMOD. BCNT continues
incrementing as it counts BT clocks until an overflow occurs. An overflow causes the BT interrupt request flag (IRQB) to be set to "1" to signal that the designated time interval has elapsed. An interrupt request is then generated, BCNT is cleared to "0", and counting continues from 00H. Oscillation Stabilization Interval Control Setting bits 2-0 of the BMOD register determines the time interval (also referred to as 'wait time') required to stabilize clock signal oscillation when power-down mode is released by an interrupt. When a RESET signal is generated, the standard stabilization interval for system clock oscillation following a RESET is 31.3ms at 4.19 MHz.
"CLEAR" SIGNAL CLEAR BCNT CLEAR IRQB INTERRUPT REQUEST
BITS INSTRUCTION 4
BMOD.3 BMOD.2 BMOD.1 BMOD.0 CLOCK BCNT SELECTOR
OVERFLOW
IRQB
1-BIT R/W
8
CLOCK INPUT
CPU CLOCK START SIGNAL (POWER-DOWN RELEASE)
Figure 27. Basic Timer Circuit Diagram
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PRODUCT SPECIFICATION
BASIC TIMER MODE REGISTER (BMOD) The basic timer mode register, BMOD, is used to select input frequency and oscillation stabilization time. The most significant bit of the BMOD register,
BMOD.3, is used to restart the basic timer. When BMOD.3 is set to "1", the contents of the BT counter register (BCNT) and the BT interrupt request flag (IRQB) are both cleared to "0", and timer operation is restarted.
Table 19. Basic Timer Mode Register (BMOD) Organization (4-Bit W) BMOD.3 1 BMOD.2 0 0 1 1 BMOD.1 0 1 0 1 BMOD.0 0 1 1 1 Basic Timer Enable/Disable Control Bit Start basic timer; clear IRQB, BCNT, and BMOD.3 to "0". Basic Timer Input Clock fx/212 (1.02 kHz) fx/29 (8.18 kHz) fx/27 (32.7 kHz) fx/25 (131 kHz) Oscillation Stabilization 2 20/fx (250 ms) 2 17/fx (31.3 ms) 2 15/fx (7.82 ms) 2 13/fx (1.95 ms)
NOTES: 1. Clock frequencies and stabilization intervals assume a system oscillator clock frequency (fx) of 4.19 MHz. 2. fx = system clock frequency. 3. Oscillation stabilization time is the time required to stabilize clock signal oscillation after Stop mode is released. 4. The standard stabilization time for system clock oscillation following a RESET is 31.3 ms at 4.19 MHz. 5. BMOD.3 is bit addressable.
BASIC TIMER COUNTER (BCNT) BCNT is an 8-bit counter register for the basic timer. When BCNT has incremented to hexadecimal 'FFH', it is cleared to '00H' and an overflow is generated. The overflow causes the interrupt request flag, IRQB, to be set to "1". When the interrupt request is generated, BCNT immediately resumes counting incoming clock signals.
NOTE Always execute a BCNT read operation twice to eliminate the possibility of reading unstable data while the counter is incrementing. If, after two consecutive reads, the BCNT values match, you can select the latter value as valid data. Until the results of the consecutive reads match, however, the read operation must be repeated until the validation condition is met.
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PRODUCT SPECIFICATION
KS57C0002 /0004 MICROCONTROLLER
PROGRAMMING TIP -- Using the Basic Timer
1. To read the basic timer count register (BCNT): BITS SMB LD LD LD CPSE JR EMB 15 EA,BCNT YZ,EA EA,BCNT EA,YZ BCNTR
BCNTR
2. When Stop mode is released by an interrupt, set the oscillation stabilization interval to 31.3 ms: BITS SMB LD LD STOP NOP NOP NOP EMB 15 A,#0BH BMOD,A
; ;
Wait time is 31.3 ms Set stop power-down mode
CPU OPERATION
NORMAL OPERATING MODE
STOP MODE
IDLE MODE (31.3 ms)
NORMAL OPERATING MODE
STOP INSTRUCTION
STOP MODE IS RELEASED BY INTERRUPT
3. To set the basic timer interrupt interval time to 1.95 ms (at 4.19 MHz): BITS SMB LD LD EI BITS EMB 15 A,#0FH BMOD,A IEB ; Basic timer interrupt enable flag is set to "1"
4. Clear BCNT and the IRQB flag and restart the basic timer: BITS SMB BITS EMB 15 BMOD.3
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PRODUCT SPECIFICATION
8-BIT TIMER/COUNTER 0 (TC0)
Timer/counter 0 (TC0) is used to count system 'events' by identifying the transition (high-to-low or low-to-high) of incoming square wave signals. To indicate that an event has occurred, or that a specified time interval has elapsed, TC0 generates an interrupt request. By counting signal transitions and comparing the current counter value with the reference register value, TC0 can be used to measure specific time intervals.
Timer/counter 0 can supply a clock signal to the clock selector circuit of the serial I/O interface for data shifter and clock counter operations. (These internal SIO operations are controlled in turn by the SIO mode register, SMOD). This clock generation function lets you adjust data transmission rates across the serial interface.
P3.0 TCL0
CLOCKS (fx/210, fx/2 6, fx/2 4, fx) 8
TMOD0.7 TMOD0.6 8 TMOD0.5 TMOD0.4 TMOD0.3 TMOD0.2 TMOD0.1 TMOD0.0 IRQT0 CLEAR SET CLEAR TOL0 INVERTED CLOCK SELECTOR TCNT0 8-BIT COMPARATOR CLEAR
8 TREF0
SERIAL I/O TCLO0 PM3.1 P3.1 LATCH TOE0
Figure 28. TC0 Circuit Diagram PROGRAMMABLE TIMER/COUNTER FUNCTION Timer/counter 0 can generate interrupt requests at various intervals, based on the selected system clock frequency. The reference register, TREF0, stores the value for the number of clock pulses to be generated between interrupt requests. The counter register, TCNT0, counts the incoming clock pulses, which are compared to the TREF0 value as TCNT0 is incremented. When TREF0 = TCNT0, the TC0 interrupt request flag (IRQT0) is set to "1", the status of TOL0 is inverted, and the interrupt is generated. The content of TCNT0 is then cleared to 00H, and TC0 continues counting. EVENT COUNTER FUNCTION Timer/counter 0 can be used to monitor or detect system 'events' by using the external clock input at the TCL0 pin (I/O port 3.0) as the counter source. To activate the TC0 event counter function, P3.0/TCL0 must be set to input mode. With the exception of the different TMOD0.4-TMOD0.6 settings, the operation sequence for TC's event counter function is identical to its programmable timer/counter function.
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PRODUCT SPECIFICATION
KS57C0002 /0004 MICROCONTROLLER
TC0 CLOCK FREQUENCY OUTPUT Using timer/counter, you can output a modifiable clock frequency to the TC0 clock output pin, TCLO0. To enable the output to the TCLO0/P3.1, the pin must be set to output mode when the timer output enable flag (TOE0) has been enabled.
PROGRAMMING TIP -- TC0 Signal Output to the TCLO0 Pin
Output a 30 ms pulse width signal to the TCLO0 pin: BITS SMB LD LD LD LD LD LD BITR BITS EMB 15 EA,#79H TREF0,EA EA,#4CH TMOD0,EA EA,#20H PMG1,EA P3.1 TOE0
; ;
P3.1 Output mode P3.1 clear
By selecting an external clock source, you can divide the incoming clock signal by the TREF0 value and then output this modified clock frequency to the TCLO0 pin.
PROGRAMMING TIP -- External TCL0 Clock Output to the TCLO0 Pin
Output external TCL0 clock pulse to the TCLO0 pin (divide by four):
EXTERNAL (TCL0) CLOCK PULSE
TCLO0 OUTPUT PULSE
BITS SMB LD LD LD LD LD LD BITR BITS
EMB 15 EA,#01H TREF0,EA EA,#0CH TMOD0,EA EA,#20H PMG1,EA P3.1 TOE0
; ;
P3.1 Output mode P3.1 clear
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TC0 MODE REGISTER (TMOD0) TMOD0 is the 8-bit mode control register for timer/counter 0. When TMOD0.3 is set to "1", the contents of TCNT0, IRQT0, and TOL0 are cleared, counting starts from 00H, and TMOD0.3 is automatically reset to "0" for normal TC0 operation. When TC0 operation stops (TMOD0.2 = "0"), the contents of the TC0 counter register, TCNT0, are retained until TC0 is re-enabled.
Table 20. TC0 Mode Register (TMOD0) Organization (8-Bit W) Bit Name TMOD0.7 TMOD0.6 TMOD0.5 TMOD0.4 TMOD0.3 1 Clear TCNT0, IRQT0, and TOL0. Then immediately resume counting. (This bit is automatically cleared to "0" when counting resumes.) Disable timer/counter; retain TCNT0 contents Enable timer/counter Value always "0" LSB value always "0" F90H 0,1 Specify input clock edge and internal frequency Setting 0 Resulting TC0 Function MSB value always logic zero F91H Address
TMOD0.2 TMOD0.1 TMOD0.0
0 1 0 0
Table 21. TMOD0.6, TMO0.5, and TMOD0.4 Bit Settings TMOD0.6 0 0 1 1 1 1 TMOD0.5 0 0 0 0 1 1 TMOD0.4 0 1 0 1 0 1 Resulting Counter Source and Clock Frequency External clock input (TCL0) on rising edges External clock input (TCL0) on falling edges fx/210 = 4.09 kHz fx /26 = 65.5 kHz fx/24 = 262 kHz fx = 4.19 MHz
NOTE: 'fx' = system clock
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PRODUCT SPECIFICATION
KS57C0002 /0004 MICROCONTROLLER
PROGRAMMING TIP -- Restarting TC0 Counting Operation
1. Set TC0 timer interval to 4.09 kHz: BITS SMB LD LD EI BITS EMB 15 EA,#4CH TMOD0,EA IET0
2. Clear TCNT0, IRQT0, and TOL0. Then, restart the TC0 counting operation: BITS SMB BITS EMB 15 TMOD0.3
TC0 REFERENCE REGISTER (TREF0) TREF0 is used to store a reference value to be compared to the incrementing TCNT0 register in order to identify an elapsed time interval. Use the following formula to calculate the correct value to load to the TREF0 reference register: TC0 timer interval = (TREF0 value + 1) x 1 TMOD0frequencysetting
PROGRAMMING TIP -- Setting a TC0 Timer
Interval To set a 30 ms timer interval for TC0, given fx = 4.19MHz, follow these steps. 1. Select the timer/counter mode register with a maximum setup time of 62.5 ms (assume that the TC0 counter clock = fx/2 10, and TREF0 is FFH): 2. Calculate the TREF0 value: 30 ms = TREF0value+1 4.09kHz 30ms = 122.9 = 7AH 244s
(assuming a TREF0 value 0) TC0 OUTPUT ENABLE FLAG (TOE0) The 1-bit timer/counter 0 output enable flag TOE0 controls output from TC0 to the TCLO0 pin. F92H 0 TOE0 0 1-Bit R/W 0
TREF0 + 1 =
TREF0 value = 7AH - 1 = 79H 3. Load the value 79H to the TREF0 register: BITS SMB LD LD LD LD EMB 15 EA,#79H TREF0,EA EA,#4CH TMOD0,EA
When you set the TOE0 flag to "1", the contents of TOL0 can be output to the TCLO0 pin.
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PRODUCT SPECIFICATION
WATCH TIMER
Watch timer functions include real-time and watchtime measurement and interval timing for the system clock. It is also used as a clock source for generating buzzer output. To start the watch timer, set bit 2 of the watch timer mode register, WMOD.2, to "1". The watch timer starts, the interrupt request flag IRQW is automatically set to "1", and interrupt requests commence in 0.5second intervals. Because the watch timer functions as a quasi-interrupt instead of a vectored interrupt, the IRQW flag should be cleared to "0" by program
software as soon as a requested interrupt service routine has been executed. The watch timer can generate a steady 2 kHz, 4 kHz, 8 kHz, or 16 kHz signal to the BUZ pin. To generate a BUZ signal, clear the output latch for I/O port 6.3 to "0" and set the port 6.3 output mode flag (PM6.3) to output mode. By setting WMOD.1 to "1", the watch timer functions in high-speed mode, generating an interrupt every 3.91 ms. High-speed mode is useful for timing events during program debugging sequences.
P6.3 LATCH WMOD.7 0 WMOD.5 8 WMOD.4 0 WMOD.2 WMOD.1 0 fw/2 7
fw/16 (2 KHz)
PM6.3
BUZ
MUX
fx = SYSTEM CLOCK fw = WATCH TIMER FREQUENCY
ENABLE / DISABLE
fw/8 (4 kHz) fw/4 (8 kHz)
fw/2 (16 kHz)
SELECTOR CIRCUIT
IRQW
FREQUENCY CLOCK DIVIDING SELECTOR 32.768 kHz CIRCUIT fw
fw/214 (2 Hz)
GND fx/128 Figure 29. Watch Timer Circuit Diagram
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PRODUCT SPECIFICATION
KS57C0002 /0004 MICROCONTROLLER
WATCH TIMER MODE REGISTER (WMOD) The watch timer mode register WMOD is used to select specific watch timer operations. Table 22. Watch Timer Mode Register (WMOD) Organization (8-Bit W) Bit Name WMOD.7 Values 0 1 WMOD.6 WMOD.5 - .4 0 0 1 1 WMOD.3 WMOD.2 WMOD.1 WMOD.0 "0" 0 1 0 1 0 "0" 0 1 0 1 Function Disable buzzer (BUZ) signal output Enable buzzer (BUZ) signal output Always "0" 2 kHz buzzer (BUZ) signal output 4 kHz buzzer (BUZ) signal output 8 kHz buzzer (BUZ) signal output 16 kHz buzzer (BUZ) signal output Always "0" Disable watch timer; clear frequency dividing circuits Enable watch timer Normal mode; sets IRQW to 0.5 s High-speed mode; sets IRQW to 3.91 ms Always "0" F88H F89H Address
NOTE: System clock frequency (fx) is assumed to be 4.19 MHz.
PROGRAMMING TIP -- Using the Watch Timer
1. Select a 0.5 second interrupt, and 2 kHz buzzer enable: BITS SMB LD LD BITR LD LD BITS EMB 15 EA,#80H PMG3,EA P6.3 EA,#84H WMOD,EA IEW
; ;
P6.3 Output mode Clear P6.3 output latch
2. Sample real-time clock processing method: CLOCK BTSTZ RET * * * IRQW ; ; ; ; 0.5 second check No, return Yes, 0.5 second interrupt generation Increment HOUR, MINUTE, SECOND
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PRODUCT SPECIFICATION
COMPARATOR
Port 2 can be used as a analog input port for the 4channel comparator block. The reference voltage for the comparator can be supplied either internally or externally at P2.3. When internal reference voltage is used, four channels (P2.0-P2.3) are used for analog inputs and the internal reference voltage is varies at 16 levels. If
an external reference voltage is input at P2.3, the other three pins (P2.0-P2.2) in port 2 are used for analog input. Unused port 2 pins must be connected to VDD. When a conversion is completed, the result is saved in the comparison result register CMPREG. The initial values of the CMPREG are undefined and the comparator operation is disabled by a RESET.
P2.0 / CIN0 M P2.1 / CIN1 U P2.2 / CIN2 X P2.3 / CIN3 VREF (EXTERNAL) M INTERNAL BUS U VDD X CMOD.7 CMOD.6 1/2R R R M U X 1/2R VREF (INTERNAL) CMOD.5 0 CMOD.3 CMOD.2 CMOD.1 CMOD.0 8
+ -
COMPARISON RESULT REGISTER (CMPREG)
4
Figure 30 Comparator Circuit Diagram
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PRODUCT SPECIFICATION
KS57C0002 /0004 MICROCONTROLLER
COMPARATOR MODE REGISTER (CMOD) The comparator mode register (CMOD) is used to set the operation mode of the comparator. Based on the CMOD.5 bit setting, an internal or an external reference voltage is input for the comparator, as follows: When CMOD.5 is "0": -- A reference voltage is selected by the CMOD.0 to CMOD.3 bit settings. -- P2.0 to P2.3 are used as analog input pins. -- The internal digital-to-analog converter generates 16 reference voltages. -- The comparator can detect a 150 mV difference between the reference voltage and analog input voltages. -- Comparator results are written into 4-bit comparison result register (CMPREG).
When CMOD.5 is set to "1": -- External reference voltage is supplied from P2.3/CIN3. -- P2.0 to P2.2 are used as the analog input pins. -- The comparator can detect a 150 mV difference between the reference voltage and analog input voltages. -- Bits 0-2 in the CMPREG register contain the results (the content of bit 3 is not used). Bit 6 in the CMOD register controls conversion time while bit 7 enables or disables comparator operation to reduce power consumption.
CMOD.7 CMOD.6 CMOD.5
0
CMOD.3 CMOD.2
CMOD.1 CMOD.0
FD6H-FD7H
Reference voltage (VREF) selection: VDD x (n + 0.5)/16, n = 0 to 15 1: CIN3; external reference, CIN0-2; analog input 0: Internal reference, CIN0-3; analog input 1: Conversion time (4 x 24 /fx, 15.2 s @4.19MHz) 0: Conversion time (4 x 27 /fx, 121.6 s @4.19MHz)
1: Comparator operation enable 0: Comparator operation disable
Figure 31. Comparator Mode Register Organization PORT 2 MODE REGISTER (P2MOD) P2MOD register settings determine if port 2 is used for analog or digital input. FE2H P2MOD.3 P2MOD.2 P2MOD.1 4-Bit W P2MOD.0 When a P2MOD bit is set to "1", the corresponding pin is configured as a digital input pin. When it is "0", the corresponding pin is configured as an analog input: P2MOD.0 for P2.0, P2MOD.1 for P2.1, P2MOD.2 for P2.2, and P2MOD.3 for P2.3.
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PRODUCT SPECIFICATION
COMPARATOR OPERATION The comparator compares analog voltage input at CIN0-CIN3 with an external or internal reference voltage (VREF) that is selected by CMOD register. The result is written to the comparison result register CMPREG at address FD4H.
The comparison result is calculated as follows: If "1" If "0" Analog input voltage VREF + 150 mV Analog input voltage VREF - 150 mV
To obtain a comparison result, the data must be read out from the CMPREG register after VREF is updated by changing the CMOD value after a conversion time has elapsed.
ANALOG INPUT VOLTAGE (CIN0-3) REFERENCE VOLTAGE (VREF) COMPARISON TIME (CMPCLK x 4) COMPARATOR CLOCK (CMPCLK, fx/16, fx/128)
COMPARISON START COMPARISON RESULT (CMPREG) UNKNOWN
COMPARISON END
1
1
0
Figure 32. Conversion Characteristics
PROGRAMMING TIP -- Programming the Comparator
The following program example converts the analog voltage input at CIN0-CIN2 pins into 4-bit digital code. BITR LD LD LD WAIT LD LD A,#0H INCS JR LD LD EMB A,#0H P2MOD,A EA,#8XH CMOD,EA A WAIT A,CMPREG P4,A
; ; ;
Analog input selection (CIN0-CIN3) x = 0-F, comparator enable Internal reference, conversion time (121.6 s)
; ;
Read the result Output the result from port 4
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KS57C0002 /0004 MICROCONTROLLER
SERIAL I/O INTERFACE
Using the serial I/O interface, you can exchange 8-bit data with an external device. The serial interface can run off an internal or an external clock source, or the TOL0 signal that is generated by the 8-bit timer/counter 0, TC0. If you use the TOL0 clock signal, you can modify its frequency to adjust the serial data transmission rate.
INTERNAL BUS 8 LSB or MSB first SO SI SBUF (8-BIT)
R
CLK D CLK
SCK
TOL0 fx/210 fx/2 CLOCK SELECTOR
Q IRQS
R Q S CLK
Q0 Q1 Q2 3-BIT COUNTER CLEAR
SMOD.7
SMOD.6 SMOD.5
- 8
SMOD.3 SMOD.2
SMOD.1 SMOD.0
Figure 33. Serial I/O Interface Circuit Diagram
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PRODUCT SPECIFICATION
SERIAL I/O MODE REGISTER (SMOD) The serial I/O mode register (SMOD) specifies the operation mode of the serial interface. SMOD register settings enable you to select either MSB-first or LSBfirst serial transmission, and to operate in transmitand-receive mode or receive-only mode. When SMOD.3 is set to "1", the contents of the serial interface interrupt request flag, IRQS, and the 3-bit serial clock counter are cleared, and SIO operations are initiated. When the SIO transmission starts, SMOD.3 is cleared to "0".
SERIAL I/O BUFFER REGISTER (SBUF) When the serial interface operates in transmit-andreceive mode (SMOD.1 = "1"), transmit data in the SIO buffer register are output to the SO pin at the rate of one bit for each falling edge of the SIO clock. Receive data is simultaneously input from the SI pin to SBUF at the rate of one bit for each rising edge of the SIO clock. When receive-only mode is used, incoming data is input to the SIO buffer at the rate of one bit for each rising edge of the SIO clock. SBUF can be read or written using 8-bit RAM control instructions.
Table 23. SIO Mode Register (SMOD) Organization (8-Bit W) SMOD.0 SMOD.1 SMOD.2 0 1 0 1 0 1 SMOD.3 SMOD.4 SMOD.7 0 1 0 SMOD.6 0 Most significant bit (MSB) is transmitted first Least significant bit (LSB) is transmitted first Receive-only mode; output buffer is off Transmit-and-receive mode Disable the data shifter and clock counter; retain contents of IRQS flag when serial transmission is halted Enable the data shifter and clock counter; set IRQS flag to "1" when serial transmission is halted Clear IRQS flag and 3-bit clock counter to "0"; initiate transmission and then reset this bit to "0"; this bit is also bit-addressable. Bit not used; value is always "0" SMOD.5 0 Clock Selection External clock at SCK pin R/W Status of SBUF SBUF is enabled when SIO operation is halted or when SCK goes high. Enable SBUF read/write SBUF is enabled when SIO operation is halted or when SCK goes high.
0 0 1
0 1 0
1 x 0
Use TOL0 clock from TC0 CPU clock: fx/4, fx/8, fx/64 4.09 kHz clock: fx/210
1
1
1
262 kHz clock: fx/2 4
NOTES: 1. 'fx' = system clock; 'x' means 'don't care.' 2. kHz frequency ratings assume a system clock (fx) running at 4.19 MHz. 3. The SIO clock selector circuit cannot select a fx/2 4 clock if the CPU clock is fx/64.
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PRODUCT SPECIFICATION
KS57C0002 /0004 MICROCONTROLLER
SCK
SI DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
SO
DO7
DO6
DO5
DO4
DO3
DO2
DO1
DO0
IRQS SET SMOD.3
TRANSMIT COMPLETE
Figure 34. SIO Timing in Transmit/Receive Mode
SCK
SI DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
SO
HIGH IMPEDANCE
IRQS SET SMOD.3
TRANSMIT COMPLETE
Figure 35. SIO Timing in Receive-Only Mode
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PRODUCT SPECIFICATION
PROGRAMMING TIP -- Setting Transmit/Receive Modes for Serial I/O
1. Transmit the data value 48H through the serial I/O interface using an internal clock frequency of fx/24 and in MSB-first mode: BITS SMB LD LD LD LD LD LD EMB 15 EA,#03H PMG1,EA EA,#48H SBUF,EA EA,#0EEH SMOD,EA
; P0.0 / SCK and P0.1 / SO Output ; ; ; SIO data transfer
PROGRAMMING TIP -- Setting Transmit/Receive Modes for Serial I/O (Continued)
SCK / P0.0
SO / P0.1
EXTERNAL DEVICE
KS57C0002
2. Use CPU clock to transfer and receive serial data at high speed: BITR LD LD LD LD LD LD BITR BTSTZ JR LD LD EMB EA,#03H PMG1,EA EA,TDATA SBUF,EA EA,#4FH SMOD,EA IES IRQS STEST EA,SBUF RDATA,EA
; P0.0 / SCK and P0.1 / SO Output, P0.2 / SI Input ; TDATA address = Bank0(20H-7FH) ; SIO start ; SIO Interrupt Enable
STEST
; RDATA address = Bank0 (20H-7FH)
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PRODUCT SPECIFICATION
KS57C0002 /0004 MICROCONTROLLER
PROGRAMMING TIP -- Setting Transmit/Receive Modes for Serial I/O (Continued)
3. Transmit and receive an internal clock frequency of 4.09 kHz (at 4.19 MHz) in LSB-first mode: BITR LD LD LD LD LD LD EI BITS * * * PUSH PUSH BITR LD XCH LD BITS POP POP IRET EMB EA,#03H PMG1,EA EA,TDATA SBUF,EA EA,#8FH SMOD,EA IES
; P0.0 / SCK and P0.1 / SO Output, P0.2 / SI Input ; TDATA address = Bank0 (20H-7FH) ; SIO start ; SIO Interrupt Enable
INTS
SB EA EMB EA,TDATA EA,SBUF RDATA,EA SMOD.3 EA SB
; Store SMB, SRB ; Store EA ; ; ; ; ; EA Transmit data TDATA address = Bank0 (20H-7FH) Transmit data Receive data RDATA address = Bank0 (20H-7FH) SIO start
SCK / P0.0
SO / P0.1 SI / P0.2 KS57C0002
EXTERNAL DEVICE
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PRODUCT SPECIFICATION
PROGRAMMING TIP -- Setting Transmit/Receive Modes for Serial I/O (Continued)
4. Transmit and receive an external clock in LSB-first mode: BITR LD LD LD LD LD LD EI BITS * * * PUSH PUSH BITR LD XCH LD BITS POP POP IRET EMB EA,#02H PMG1,EA EA,TDATA SBUF,EA EA,#0FH SMOD,EA IES
; P0.1 / SO Output, P0.0 / SCK and P0.2/SI Input ; TDATA address = Bank0 (20H-7FH) ; SIO start ; SIO Interrupt Enable
INTS
SB EA EMB EA,TDATA EA,SBUF RDATA,EA SMOD.3 EA SB
; Store SMB, SRB ; Store EA ; ; ; ; ; EA Transmit data TDATA address = Bank0 (20H-7FH) Transmit data Receive data RDATA address = Bank0 (20H-7FH) SIO start
SCK / P0.0
SO / P0.1 SI / P0.2 KS57C0002
EXTERNAL DEVICE
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PRODUCT SPECIFICATION
KS57C0002 /0004 MICROCONTROLLER
ELECTRICAL DATA
Table 24. Absolute Maximum Ratings (TA = 25 C) Parameter Supply Voltage Input Voltage Symbol V DD V I1 Ports 4, 5 Conditions -- CMOS push-pull Open-drain V I2 Output Voltage Output Current High Output Current Low VO IOH IOL All I/O ports except 4 and 5 -- One I/O port active All I/O ports active Ports 0, 3, and 6 Ports 4 and 5 All ports, total Operating Temperature Storage Temperature TA Tstg -- -- Rating - 0.3 to + 7.0 - 0.3 to VDD + 0.3 - 0.3 to + 9 - 0.3 to VDD + 0.3 - 0.3 to VDD + 0.3 -5 - 15 5 30 + 100 - 40 to + 85 - 65 to + 150
C C
Units V V
V mA mA
Table 25. D.C. Electrical Characteristics (TA = - 40 C to + 85 C, VDD = 2.7 V to 6.0 V) Parameter Input High Voltage Symbol V IH1 V IH2 V IH3 Input Low Voltage V IL1 V IL2 V IL3 Output High Voltage V OH Conditions Ports 4 and 5 Ports 0, 1, 2, 3, 6, and RESET X in and Xout Ports 4 and 5 Ports 0, 1, 2, 3, 6, X in and Xout V DD = 4.5 V to 6.0 V IOH = - 1 mA Ports 0, 3, 4, 5, 6 V DD = 4.5 V to 6.0 V IOH = - 3.0 mA Ports 0, 3, 4, 5, 6
* The value is 0.2V at KS57C0002 or 0.4V at KS57C0004.
Min 0.7V DD 0.8V DD V DD - 0.5 --
Typ -- -- -- --
Max V DD V DD V DD 0.3V DD 0.2V DD *
Units V
V
and RESET
V DD - 1.0 --
--
V
V DD - 2.0
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PRODUCT SPECIFICATION
Table 25. D.C. Electrical Characteristics (Continued) (TA = - 40 C to + 85 C, VDD = 2.7 V to 6.0 V) Parameter Output Low Voltage Symbol V OL Conditions V DD = 4.5 V to 6.0 V IOL = 15 mA Ports 4 and 5 only V DD = 4.5 V to 6.0 V IOL = 1.6 mA Ports 0, 3, 6 only V DD = 4.5 V to 6.0 V IOL = 4.0 mA Ports 0, 3, 6 only Input High Leakage Current ILIH1 V IN = VDD All input pins except Xin and Xout V IN = VDD X in and Xout V IN = 9 V Ports 4 and 5 are open-drain V IN = 0 V All input pins except Xin, Xout and -- -- -- -- Min -- Typ 0.4 Max 2 Units V
--
0.4
2
3
A
ILIH2 ILIH3 Input Low Leakage Current ILIL1
20 10 -3 A
RESET
ILIL2 Output High Leakage Current ILOH1
V IN = 0 V X in and Xout V O = VDD All output pins except for port 4 and port 5 VO = 9 V Ports 4 and 5 are open-drain VO = 0 V V IN = 0 V; VDD = 5 V 10% Port 0, 1, 3, 6 V IN = 0 V; VDD = 3 V 10% Port 0, 1, 3, 6 -- -- -- --
- 20 3 A
ILOH2 Output Low Leakage Current Pull-Up Resistor ILOL
10 -3 A
RL1
15 30 100 200
40
80 200
K
RL2
V IN = 0 V; VDD = 5 V 10%
RESET RESET
230 490
400 800
K
V IN = 0 V; VDD = 3 V 10%
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KS57C0002 /0004 MICROCONTROLLER
Table 25. D.C. Electrical Characteristics (Concluded) (TA = - 40 C to + 85 C, VDD = 2.7 V to 6.0 V) Parameter Supply Current (1) Symbol IDD1 Conditions V DD = 5 V 10% (2) 4.19 MHz crystal oscillator C1 = C2 = 22 pF V DD = 3 V 10% (3) 4.19 MHz crystal oscillator C1 = C2 = 22 pF IDD2 Idle mode; VDD = 5 V 10% 4.19 MHz crystal oscillator C1 = C2 = 22 pF Idle mode; VDD = 3 V 10% 4.19 MHz crystal oscillator C1 = C2 = 22 pF IDD3 Stop mode V DD = 5 V 10% Stop mode V DD = 3 V 10% -- Min -- Typ 2.5 Max 8 Units mA
0.62
1.2
1.2
1.8
mA
0.58
1.0
0.5 0.3
5 3
A
NOTES: 1. The currents in the following circuits are not included; on-chip pull-up resistors, output port drive currents and comparator. 2. For high-speed controller operation, set the PCON register to 0011B. 3. For low-speed controller operation, set the PCON register to 0000B.
CPU CLOCK 1.0475 MHz 1.00 MHz 750 kHz 500 kHz 250 kHz
15.6 kHz
1
2
3
4
5
6
7
SUPPLY VOLTAGE (V) CPU CLOCK = 1/n x oscillator frequency (n = 4, 8, 64)
Figure 36. Standard Operating Voltage Range
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PRODUCT SPECIFICATION
Table 26. Oscillator Characteristics (TA = - 40 C to + 85 C, VDD = 5 V) Oscillator Ceramic Oscillator Clock Configuration
Xin Xout
Parameter Oscillation frequency (1)
Test Condition --
Min 0.4
Typ --
Max 4.5
Units MHz
C1
C2
Stabilization time (2)
After V DD reaches the minimum level of its variable range --
--
--
4
ms
Crystal Oscillator
Xin
Xout
Oscillation frequency (1)
0.4
4.19
4.5
MHz
C1
C2
Stabilization time (2) External Clock Xin input frequency (1)
V DD = 2.7 V to 4.5 V V DD = 4.5 V to 6.0 V --
-- -- 0.4
-- -- --
30 10 4.5
ms ms MHz
Xin
Xout
Xin input high and low level width (t XH , tXL) RC Oscillator (3)
Xin R Xout
-- V DD = 5 V
100 0.4
-- --
150 2
ns MHz
Oscillation frequency limitation
NOTES: 1. Oscillation frequency and X in input frequency data are for oscillator characteristics only. 2. Stabilization time is the interval required for oscillator stabilization after a reset or termination of Stop mode. 3. RC is only for the KS57C0002.
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KS57C0002 /0004 MICROCONTROLLER
Table 27. Input/Output Capacitance (TA = 25 C, VDD = 0 V ) Parameter Input Capacitance Output Capacitance I/O Capacitance Symbol CIN COUT CIO Condition f = 1 MHz; Unmeasured pins are returned to VSS Min -- -- -- Typ -- -- -- Max 15 15 15 Units pF pF pF
Table 28. Comparator Electrical Characteristics (TA = - 40 C to + 85 C, VDD = 4.0 V to 6.0 V, VSS = 0 V) Parameter Input Voltage Range Reference Voltage Range Input Voltage Accuracy Input Leakage Current Symbol -- V REF V CIN ICIN, IREF Condition -- -- -- -- Min 0 0 -- -3 Typ -- -- -- -- Max V DD V DD 150 3 Units V V mV A
Table 29. A.C. Electrical Characteristics (TA = - 40 C to + 85 C, VDD = 2.7 V to 6.0 V) Parameter Instruction Cycle Time TCL0 Input Frequency TCL0 Input High, Low Width Symbol tCY Conditions V DD = 4.5 V to 6.0 V V DD = 2.7 V to 4.5 V fTI V DD = 4.5 V to 6.0 V V DD = 2.7 V to 4.5 V tTIH, tTIL V DD = 4.5 V to 6.0 V V DD = 2.7 V to 4.5 V 0.48 1.8 800 1600 3200 3800 -- -- ns -- Min 0.95 3.8 0 -- 1 275 -- MHz kHz s Typ -- Max 64 Units s
SCK Cycle Time
tKCY
V DD = 4.5 V to 6.0 V; Input V DD = 4.5 V to 6.0 V; Output V DD = 2.7 V to 4.5 V; Input V DD = 2.7 V to 4.5 V; Output
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PRODUCT SPECIFICATION
Table 29. A.C. Electrical Characteristics (Continued) (TA = - 40 C to + 85 C, VDD = 2.7 V to 6.0 V) Parameter Symbol tKH , tKL Conditions V DD = 4.5 V to 6.0 V; Input V DD = 4.5 V to 6.0 V; Output V DD = 2.7 V to 4.5 V; Input V DD = 2.7 V to 4.5 V; Output SI Setup Time to SCK High SI Hold Time to SCK High Output Delay for SCK to SO tSIK Input Output tKSI Input Output tKSO V DD = 4.5 V to 6.0 V; Input V DD = 4.5 V to 6.0 V; Output V DD = 2.7 V to 4.5 V; Input V DD = 2.7 V to 4.5 V; Output Interrupt Input High, Low Width tINTH, tINTL INT0 INT0, INT1, KS0-KS2 Min 400 tKCY /2 - 50 1600 tKCY /2 - 150 100 150 400 400 -- -- 300 250 1000 1000 ns -- -- ns -- -- ns Typ -- Max -- Units ns
SCK High, Low
Width
*
10 10
--
--
s
RESET Input
Width
Low
tRSL
Input
--
--
s
*
The minimum value for INT0 is based on a clock of 2tCY or 128/fx as assigned by the IMOD0 register setting.
0.8 VDD MEASUREMENT POINTS
0.8 VDD
0.2 VDD
0.2 VDD
Figure 37. A.C. Timing Measurement Points (Except for Xin)
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KS57C0002 /0004 MICROCONTROLLER
Table 30. RAM Data Retention Supply Voltage in Stop Mode (TA = - 40 C to + 85 C) Parameter Data Retention Supply Voltage Data Retention Supply Current Release Signal Set Time Oscillation Stabilization Time (1) Symbol V DDDR IDDDR tSREL tWAIT Condition -- -- -- When released by RESET When released by interrupt Min 2.0 -- 0 -- -- Typ -- 0.1 -- 2 17/fx
(2)
Max 6.0 10 -- -- --
Units V A ms ms ms
NOTES: 1. During oscillation stabilization time, CPU operation must be stopped to avoid instability during oscillator startup. 2. The basic timer causes a delay of 2 17/fx after a reset. INTERNAL RESET OPERATION STOP MODE DATA RETENTION MODE IDLE MODE OPERATING MODE
VDD VDDDR
EXECUTION OF STOP INSTRUCTION
RESET
tWAIT tSREL Figure 38. Stop Mode Release Timing When Initiated By RESET
IDLE MODE STOP MODE DATA RETENTION MODE NORMAL OPERATING MODE
VDD VDDDR
EXECUTION OF STOP INSTRUCTION
tSREL
tWAIT
POWER-DOWN MODE TERMINATING SIGNAL (INTERRUPT REQUEST)
Figure 39. Stop Mode Release Timing When Initiated By Interrupt Request
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PRODUCT SPECIFICATION
1 / fx
tXL
tXH
Xin
VDD - 0.5 V
0.4 V
Figure 40 Clock Timing Measurement at Xin
1 / fTI
tTIL
TCL0
tTIH
0.8 VDD 0.2 VDD
Figure 41. TCL0 Timing
tRSL
RESET
0.2 VDD
Figure 42. Input Timing for tINTL
RESET Signal
tINTH
INT0, 1 KS0 to KS2
0.8 VDD 0.2 VDD
Figure 43. Input Timing for External Interrupts
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KS57C0002 /0004 MICROCONTROLLER
tCKY tKL tKH
0.8 VDD 0.2 VDD
SCK
tSIK tKSI
0.8 VDD SI INPUT DATA 0.2 VDD
tKSO
SO OUTPUT DATA
Figure 44. Serial Data Transfer Timing
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PRODUCT SPECIFICATION
CHARACTERISTIC CURVES
NOTE The characteristic values shown in the following graphs are based on actual test measurements. They do not, however, represent guaranteed operating values. IDD1 vs. FREQUENCY (CPU CLOCK = fx/4, fx = 1, 2, 4.2 MHz)
4
OPERATING CURRENT IDD1 (mA)
3.5 3 2.5 2 1.5 1 0.5 0 0.0 1.0 2.0 3.0 4.0 5.0 VDD = 3.3 V VDD = 5.5 V
FREQUENCY (MHz) Figure 45. Frequency VS. IDD1
IDD2 vs. FREQUENCY (CPU CLOCK = fx/4, fx/64, fx = 4.2 MHz)
1.5
IDLE CURRENT IDD2 (mA)
VDD = 5.5 V 1
0.5
VDD = 3.3 V
0 0.0 1.0 2.0 3.0 4.0 5.0
FREQUENCY (MHz) Figure 46. Frequency VS. IDD2
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IDD1 vs. VDD (CPU CLOCK = fx/4, fx/64, fx = 4.2 MHz) OPERATING CURRENT IDD1 (mA)
4 3.5 3 2.5 2 1.5 1 0.5 0 3.0 4.0 5.0 6.0 7.0 fx/64 fx/4
POWER SUPPLY VOLTAGE VDD (V)
Figure 47. VDD VS. IDD1
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PRODUCT SPECIFICATION
NOTES
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PRODUCT SPECIFICATION
KS57C0002 /0004 MICROCONTROLLER
NOTES
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